JPH0336717Y2 - - Google Patents

Info

Publication number
JPH0336717Y2
JPH0336717Y2 JP20341285U JP20341285U JPH0336717Y2 JP H0336717 Y2 JPH0336717 Y2 JP H0336717Y2 JP 20341285 U JP20341285 U JP 20341285U JP 20341285 U JP20341285 U JP 20341285U JP H0336717 Y2 JPH0336717 Y2 JP H0336717Y2
Authority
JP
Japan
Prior art keywords
screen
winding shaft
base edge
longitudinal direction
outer circumferential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP20341285U
Other languages
English (en)
Japanese (ja)
Other versions
JPS62113295U (en]
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP20341285U priority Critical patent/JPH0336717Y2/ja
Publication of JPS62113295U publication Critical patent/JPS62113295U/ja
Application granted granted Critical
Publication of JPH0336717Y2 publication Critical patent/JPH0336717Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Operating, Guiding And Securing Of Roll- Type Closing Members (AREA)
  • Specific Sealing Or Ventilating Devices For Doors And Windows (AREA)
JP20341285U 1985-12-30 1985-12-30 Expired JPH0336717Y2 (en])

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20341285U JPH0336717Y2 (en]) 1985-12-30 1985-12-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20341285U JPH0336717Y2 (en]) 1985-12-30 1985-12-30

Publications (2)

Publication Number Publication Date
JPS62113295U JPS62113295U (en]) 1987-07-18
JPH0336717Y2 true JPH0336717Y2 (en]) 1991-08-02

Family

ID=31168717

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20341285U Expired JPH0336717Y2 (en]) 1985-12-30 1985-12-30

Country Status (1)

Country Link
JP (1) JPH0336717Y2 (en])

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6881632B2 (en) 2000-12-04 2005-04-19 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS
US7049627B2 (en) 2002-08-23 2006-05-23 Amberwave Systems Corporation Semiconductor heterostructures and related methods
US7060632B2 (en) 2002-03-14 2006-06-13 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US7227176B2 (en) 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
US7250359B2 (en) 1997-06-24 2007-07-31 Massachusetts Institute Of Technology Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
US7256142B2 (en) 2001-03-02 2007-08-14 Amberwave Systems Corporation Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
US7259388B2 (en) 2002-06-07 2007-08-21 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7348259B2 (en) 2001-04-04 2008-03-25 Massachusetts Institute Of Technology Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers
US7439164B2 (en) 2002-06-10 2008-10-21 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US7594967B2 (en) 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07122388B2 (ja) * 1990-01-22 1995-12-25 三和シャッター工業株式会社 巻取装置

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7250359B2 (en) 1997-06-24 2007-07-31 Massachusetts Institute Of Technology Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
US7227176B2 (en) 1998-04-10 2007-06-05 Massachusetts Institute Of Technology Etch stop layer system
US6881632B2 (en) 2000-12-04 2005-04-19 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS
US7256142B2 (en) 2001-03-02 2007-08-14 Amberwave Systems Corporation Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
US7501351B2 (en) 2001-03-02 2009-03-10 Amberwave Systems Corporation Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
US7348259B2 (en) 2001-04-04 2008-03-25 Massachusetts Institute Of Technology Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers
US7060632B2 (en) 2002-03-14 2006-06-13 Amberwave Systems Corporation Methods for fabricating strained layers on semiconductor substrates
US7259388B2 (en) 2002-06-07 2007-08-21 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US7297612B2 (en) 2002-06-07 2007-11-20 Amberwave Systems Corporation Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes
US7414259B2 (en) 2002-06-07 2008-08-19 Amberwave Systems Corporation Strained germanium-on-insulator device structures
US7420201B2 (en) 2002-06-07 2008-09-02 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures with elevated source/drain regions
US7588994B2 (en) 2002-06-07 2009-09-15 Amberwave Systems Corporation Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain
US7439164B2 (en) 2002-06-10 2008-10-21 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US7368308B2 (en) 2002-08-23 2008-05-06 Amberwave Systems Corporation Methods of fabricating semiconductor heterostructures
US7375385B2 (en) 2002-08-23 2008-05-20 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups
US7049627B2 (en) 2002-08-23 2006-05-23 Amberwave Systems Corporation Semiconductor heterostructures and related methods
US7594967B2 (en) 2002-08-30 2009-09-29 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy

Also Published As

Publication number Publication date
JPS62113295U (en]) 1987-07-18

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